Custom engineering

The catalog is the starting point, not the limit

Most programs need something the catalog does not have — a different channel count, a connector that fits an existing chassis, a processing block that has to run in the FPGA rather than on the host. We treat that as the normal case, not as a special request.

FPGA signal processing

  • Full-bandwidth digital down-conversion and up-conversion
  • FFT, filtering and channelization
  • Analog and digital demodulation, modulation classification
  • Channel calibration and correction

Interfaces and drivers

  • JESD204B/C, SRIO, Aurora, PCIe, DDR3/4, SATA, UDP, SPI, UART, I2C
  • Windows and Linux drivers and application layers
  • Control API with source examples
  • Timing: external reference, IRIG-B, PPS

Board and system design

  • Channel count, connector and front panel changes on an existing platform
  • New carriers around a specified FPGA or converter
  • Chassis integration for PCIe, OpenVPX and standalone enclosures
  • Thermal and signal integrity analysis

Process

Six gates from requirement to release

Every custom program runs through the same review gates. You see the design at each one, and nothing moves to the next stage until the previous gate is signed off.

  1. TR1
    Requirements

    Requirements captured and turned into a business and technical proposal.

  2. TR2
    Plan and outline design

    Schedule, interfaces and block-level design agreed before anything is committed.

  3. TR3
    Hardware and software design

    Detailed design review of the board, the FPGA architecture and the host software.

  4. TR4
    Delivery test

    Signal integrity, reliability and software test against the agreed acceptance criteria.

  5. TR5
    Design freeze

    Hardware and firmware versions frozen, documentation package completed.

  6. TR6
    Release

    Production release, with change control from this point forward.

What ships with the hardware

The FPGA framework is layered into link, transport and application layers, and the architecture is open to you: the link layer handles PCIe, VPX, network and optical transport, buffering, firmware management and health monitoring, so your work sits in the application layer instead of rebuilding infrastructure. Drivers, a control API and application source examples are supplied for Windows and Linux.